This book focusses on the spacer engineering aspects of novel MOS-based device-circuit co-design in sub-20nm technology node, its process complexity, variability, and reliability issues. It comprehensively explores the FinFET/tri-gate architectures with their circuit/SRAM suitability and tolerance to random statistical variations.

Brajesh Kumar Kaushik received Ph.D. degree in 2007 from Indian Institute of Technology Roorkee, India. He served Vinytics Peripherals Pvt. Ltd., Delhi, as Research and Development Engineer in microprocessor, microcontroller, and DSP (Digital Signal Processing) processor-based system design. He joined Department of Electronics and Communication Engineering, G.B. Pant Engineering College, Pauri Garhwal, Uttarakhand, India, as Lecturer in July, 1998, where later he served as Assistant Professor from May, 2005 to May, 2006 and Associate Professor from May, 2006 to December, 2009. He joined Department of Electronics and Communication Engineering, Indian Institute of Technology Roorkee as Assistant Professor in December, 2009; where since April, 2014, he is working as Associate Professor. He has extensively published in several national and international journals and conferences of repute. He has also authored/co-authored several books and book chapters. He is reviewer of many international journals belonging to various publications such as IEEE (Institute of Electrical and Electronics Engineers), IET (Institution of Engineering and Technology), Elsevier, Springer, Taylor and Francis, Emerald, ETRI (Electronics and Telecommunications Research Institute), and PIER (Progress in Electromagnetics Research). He has served as General Chair, Technical Chair, and Keynote Speaker of many reputed international and national conferences. Dr. Kaushik is Senior Member of IEEE and member of many expert committees constituted by government and non-government organizations. He holds the position of Editor and Editor-in-Chief of various journals in the field of VLSI (Very Large Scale Integration) and microelectronics such as International Journal of VLSI Design & Communication Systems (VLSICS), AIRCC (Academy & Industry Research Collaboration Center) Publishing Corporation. He also holds the position of Editor of Microelectronics Journal (MEJ), Elsevier Inc.; Journal of Engineering, Design and Technology (JEDT), Emerald Group Publishing Limited; Journal of Electrical and Electronics Engineering Research (JEEER); and Academic Journals. He has received many awards and recognitions from the International Biographical Center (IBC), Cambridge. His name has been listed in Marquis Who's Who in Science and Engineering(R) and Marquis Who's Who in the World(R). Dr. Kaushik has been conferred with Distinguished Lecturer award of IEEE Electron Devices Society (EDS) to offer EDS Chapters with a list of quality lectures in his research domain. His research interests are in the areas of high-speed interconnects, low-power VLSI design, memory design, carbon nanotube-based designs, organic electronics, FinFET device circuit co-design, electronic design automation (EDA), spintronics-based devices, circuits, and computing, image processing, and optics and photonics based devices.

Dr. S. Dasgupta is an Associate Professor in the Department of Electronics and Communication Engineering at the Indian Institute of Technology (IIT) Roorkee, India. He received his Ph.D. degree in electronics engineering from IIT-Banaras Hindu University, Varanasi, India, in 2000. During his Ph.D. work, he carried out research in the area of effects of ionizing radiation on MOSFETs. Subsequently, he became a member of the faculty in the Department of Electronics Engineering at the Indian School of Mines, Dhanbad, India. In 2006, he joined the Department of Electronics and Communication Engineering, IIT Roorkee, as an Assistant Professor. He has authored/coauthored more than 200 research papers in peerreviewed international journals and conferences. He is a member of Institute of Electrical and Electronics Engineers (IEEE), Electron Devices Society (EDS), and Indian Society for Technical Education (ISTE) and an associate member of Institute of Nanotechnology, the United Kingdom. He has been a technical committee member of the International Conference on Micro-to-Nano since 2006; he has also been nominated as Marquis's Who's Who in Science in Engineering(R) (the United States) awarded by Marquis, 2006-2008, and has been acting as an expert member of The Global Open University, the Netherlands. He was awarded with the Erasmus Mundus Fellowship of the European Union in 2010 to work in the area of Resource Description Framework (RDF) at Politecnico Di Torino, Italy. He was a recipient of the prestigious Indo-U.S. Science and Technology Forum (IUSSTF) to work in the area of SRAM testing at the University of Wisconsin-Madison, Wisconsin, in 2011-2012. He was also awarded with the Deutscher Akademischer Austauschdienst (DAAD) Fellowship to work on analog design using reconfigurable logic at Technische Universität (TU), Dresden, Germany, in 2013. His areas of interest include nanoelectronics, nanoscale Metal Oxide Semiconductor Field-Effect Transistor (MOSFET) modeling and simulation, design and development of low-power novel devices, FinFET-based memory design, emerging devices in analog design, and development of reconfigurable logic. He has guided 10 Ph.D. scholars. Currently, he is supervising six Ph.D. candidates. He has been nominated for Indian National Academy of Engineering (INAE), Young Engineer Award. Dr. Dasgupta was a reviewer for IEEE Transactions on Electron Devices, IEEE Electron Device Letters, IEEE Transactions on Nanotechnology, Superlattice and Microstructures, International Journal of Electronics, Semiconductor Science and Technology Nanotechnology, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Microelectronic Engineering, and Microelectronic Reliability, among others. He is also a member of Technical Program Committee (TPC) for VLSI Design Conference 2016 as well as for International Symposium on VLSI Design and Test (VDAT)-2016 (IIT, Guwahati, India). He has also been a member of the technical committees of various international conferences. He has presented a tutorial at VDAT-2014 and VLSI Design Conference, Bangalore, India, in 2015, among many others.

Pankaj Kumar Pal (S'12, M'16) received a B.Tech. degree in electronics and communication engineering from Gurukul Kangri University, Haridwar, India, in 2008, an M.Tech. degree in VLSI design from the National Institute of Technology (NIT), Hamirpur, India, in 2010, and a Ph.D. degree in microelectronics and VLSI from Indian Institute of Technology (IIT) Roorkee, India, in 2016. He is currently working as an Assistant Professor in the Department of Electronics Engineering, NIT, Uttarakhand, Srinagar (Garhwal), India. His current research interests include novel MOS-based devices, FinFET parasitic extraction, Semiconductor device modeling, and low-power SRAM memory design. Dr. Pal received the Director's Medal at NIT-Hamirpur for being the branch topper in M.Tech. for 2010.